1. Field of the Invention
The present invention relates generally to clock synthesizers based on digital phase locked loops (PLL) and more particularly to clock synthesizers for serial digital communications systems which may actively be switched to using a base frequency and a forward error correction (FEC) frequency.
2. Description of the Related Art
Serial data communication systems use phase lock loop (PLL) clock generators locked to a reference frequency input (or reference clock input) to generate internal clocks. For example, serial data communication systems use PLL clock generators locked to a reference frequency input to generate local (i.e. internal) transmit clocks. In a wireless system, this clock defines both the modulation and broadcast frequency. In a wireline system, e.g. SONET/SDH, it defines the bit rate of the transmitter. All wireline systems define both a base bit rate and a forward error correction, FEC, rate. This FEC rate is necessarily higher than the basic data bit rate to allow for the inclusion of additional forward error correcting code redundancy bits into the base transmitted data, i.e. into the same time window used to send one data unit (or packet) at the basic rate. Thus, a different transceiver (with a different operating frequency) is typically needed for systems that operate at the basic bit rate without error correction code, and for systems that include FEC and thus operate at a higher bit rate.
With reference to FIG. 1, a typical PLL based frequency synthesizer 11, such as those used in high precision transceivers, use a SAW or crystal based oscillator 13. That is, oscillator 13 includes a precision variable frequency oscillator, VFO, 15 whose precision operation is based on the resonant quality of SAW or crystal resonator 17. A reference clock input provides a nominal system frequency whose long term average value is to be used for generating the local output clock. A combination phase and frequency detector, PFD, and charge pump unit 19 compares in phase and frequency the reference clock input to a feedback signal based on the output from oscillator 13, i.e. the internal output clock from VFO 15. PFD and Charge Pump unit 19 produces a control signal dependent upon the comparison result, and the control signal is used to adjust VFO 15 accordingly. A loop filter 21, such as a low pass filter, assures that the average of the comparison result is used to control the oscillator so as to avoid spurious comparison results due to, for example, momentary glitches or spikes.
Sometimes, the desired frequency of the local, i.e. internal, output clock is much higher than the frequency of the reference clock input. Therefore, a frequency divider 23 may be inserted between the output of oscillator 13 and the feedback input of PFD and Charge Pump unit 19. In this case, the reference clock input is compared to a frequency-divided, down-converted output from precision VFO 15. The filtered control signal (voltage or current) is used to set the frequency of oscillator VFO 15, which provides the local output clock signal.
Different reference clock input frequencies may be used to produce the same output clock frequency (and thus use the same SAW or Crystal resonator 17) by configuring divider block 23 to divide by different integer values. For example, it is common practice to generate a 622.08 MHz local output clock for SONET/SDH applications by using either a 622.08 MHz reference input clock or a 155.52 MHz reference input clock by setting frequency divider block 23 to a value of divide by 1 or 4, respectively. It is to be understood that if the frequency of the input reference clock (i.e. 622.08 MHz) matches the frequency of the local clock output (i.e. 622.08 MHz), frequency divider block 23 is ideally not needed.
Thus, a conventional PLL can have binary dividers in the feedback path to lock the VFO output to a reference clock input whose frequency is an integer multiple of the VFO output frequency. Another technique well known in the art is to use a dual modulus divider with a division ratio of either n or n+1 [e.g. 31 and 32] and switching between the two values dynamically in a relationship fixed by the desired output frequency. But this technique introduces spurious signals into the clock output spectrum which makes it unsuitable for precision clocks for e.g. SONET/SDH.
Although different reference clock inputs may be used to produce the same local clock output by use of appropriate frequency division in the feedback path, the same SAW or Crystal resonator 17 cannot typically be used to produce different output clocks since operation of VFO 15 is directly tied to the fixed frequency of the SAW or Crystal resonator 17. That is, a precision PLL based frequency synthesizer requires a different resonator 17 for each different output clock frequency.
It would be highly desirable to use the same transceiver module in both systems with error correction coding and in systems without error correction coding. Using a single transceiver for both systems would reduce cost in design, material procurement, and manufacturing. This would mean however, that the clock generator within the transceiver module should be able to alternate between at least two precise output operating frequencies (preferably under electronic control), and the transceiver should be capable of selectively generating either the FEC operating frequency or the base operating frequency.
Wireline systems, especially SONET/SDH long haul service, have stringent frequency stability requirements that require the use of a stable frequency reference in the oscillator. The need for stringent frequency stability means that the frequency reference is typically a precision variable frequency oscillator using a SAW resonator, a quartz crystal resonator, or other precision resonator.
With reference to FIG. 2, an example of PLL based frequency synthesizer 31 suitable for use in a precision transceiver module capable of electronically selecting between two output frequencies (i.e. a base operating frequency and an FEC operating frequency) utilizes two oscillators 13a and 13b, and a multiplexer 33 for selecting between the two oscillators 13a and 13b. All elements similar to those of FIG. 1 have similar reference characters and are explained above. Preferably, the first oscillator 13a is designed to produce a first output frequency, i.e. the base frequency, and the second oscillator 13b is designed to produce the second output frequency, i.e. the FEC frequency. As a result, duplicate VFO's 15a and 15b (each based on a different frequency resonator 17a and 17b, respectively) are required to create oscillators 13a and 13b. The frequency control voltage from PFD and Charge Pump unit 19 is fed to both variable frequency oscillators 15a and 15b, each of which oscillates at respective first and second frequencies. Multiplexer 33 selects the output according to the state of a Frequency Select control signal.
Unfortunately to maintain a high precision of operation, two different precision resonators 17a and 17b are required in this design. Precision resonators, such as 17a and 17b, are typically relatively expensive discrete components that add to system cost and space requirements. It is therefore highly desirable that the transceiver which operates at both FEC and base data rates use only one such precision resonant device to generate both output frequencies.